1. Field of the Invention
The present invention relates to a CPU contained LSI having a bus control function in a system configuration that a contained CPU and an external CPU access a common bus.
2. Description of the Related Art
In recent years, a system LSI has been complicated and large-scaled. Software for controlling the system LSI has been also progressively complicated and large-scaled. Accordingly, when a function for realizing the system LSI is mounted on a set of goods, the increase of the number of mounting steps of the software is the most serious problem.
Thus, a method that a CPU is contained in the system LSI and the control software of the system LSI is executed by the contained CPU to hide a complicated software process in the system LSI has been currently carried out. This method has been frequently used in the system LSI having interface systems which substantially serve as post-functions such as a USB, an IEEE1394, etc.
When the above-described CPU contained system LSI is mounted on a system of a set of goods, a communication between a CPU existing in the system of the set of goods and the contained CPU is necessary. A communication method is roughly classified into a method by a serial bus connection and a method of sharing a bus by parallel buses. When the communication of a large quantity of data is carried out, the bus sharing by the parallel buses is frequently employed to share a memory from the viewpoint of communication speed.
Now, referring to FIG. 6, the structure of an existing system that two CPUs share an external expansion bus to share a memory and realize a data communication will be described. As shown in FIG. 6, the system comprises a CPU contained LSI 100, a CPUb 200 and a device b201 to be controlled that is controlled by the CPUb. Further, the CPU contained LSI 100 includes a CPUa 101, a ROM 102 for storing processing programs of the CPUa, a device a 103 to be controlled that is controlled by the CPUa and a common memory 104 for carrying out a data communication between the CPUa and the CPUb.
The CPUb 200 is designed to control two devices of the device b201 to be controlled and the CPU contained system LSI 100 via an externally expanded address bus/data bus. When the CPU contained system LSI 100 is controlled, the CPU contained LSI 100 is controlled via the common memory 104.
The CPUa 101 shares the externally expanded address bus/data bus together with the CPUb 200 and reads out a processing program from the ROM 102 via this common bus. While the CPUa 101 executes the processing program, the CPUa 101 controls the device a 103 to be controlled and receives a control from the CPUb 200 via the common memory 104.
Further, the CPUa 101 and the CPUb 200 respectively have bus adjusting functions. When the CPUb 200 accesses the device b201 to be controlled or the common memory 104 by using the common bus, the CPUb 200 obtains a right for using the bus to access them in the following procedure.    (1) The CPUb 200 asserts a bus release request signal BREQ to the CPUa 101.    (2) The CPUa 101 stops an access to the common bus to assert a bus release completion signal BACK to the CPUb 200.    (3) When the CPUb 200 completes the access to the device b201 to be controlled or the common memory 104, the CPUb 200 negates the BREQ signal to the CPUa 101.    (4) After the CPUa 101 recognizes the negation of the BREQ signal, the CPUa 101 negates the BACK signal.
When the CPUa uses the common bus to access the ROM 102, the device a 103 to be controlled and the common memory 104, the CPUa sends a bus release request signal BREQ to the CPUb 200. Then, the CPUa obtains a right for using the bus and performs the same processes as those described above.
A bus adjustment for obtaining the right for using the common bus in the system that a plurality of CPUs shares the bus has a problem of priority control. Accordingly, various kinds of systems have been hitherto proposed. For example, in the publication described in JP-A-5-282246, request/permission signals of rights for using a bus by a plurality of CPUs are connected together in a ring form to exclude a fixed priority control.
However, in the structure of the above-described conventional system, the CPUa 101 ordinarily reads the processing program from the ROM 102 and executes the program. However, in this case, every time the CPUb 200 accesses the device b201 to be controlled or the common memory 104, the CPUb 200 uses the common bus, so that the CPUa 101 cannot access the ROM 102 and the CPUa 101 needs to stop a process. As a result, the processing efficiency of the CPUa 101 is disadvantageously seriously lowered.
Further, to control the CPU contained LSI 100 by the CPUb 200, the CPUb 200 needs to have the bus adjusting function using the BREQ signal and the BACK signal. Further, a selection range of the kinds of the CPUb 200 is inconveniently limited.
When the CPUb 200 is a microcomputer for entirely controlling the system, for instance, when the CPU contained system LSI 100 is the system LSI having a post-attached interface system, the operation of the CPUb 200 for controlling the entire part is frequently desired to be carried out more preferentially than that of the CPUa 101.
In the conventional structure, however, since the CPUa 101 and the CPUb 200 have the equal right to the bus, when the CPUa 101 accesses the common bus during the operation of the CPUb 200, an interruption is generated Accordingly, the CPUb 200 cannot entirely control the system and a processing efficiency as the set of goods is inconveniently deteriorated.